ISL29004
d
TABLE 2. WRITE ONLY REGISTERS
Mode3 is a sequential Mode0 and Mode1 with an internal
REGISTER
FUNCTIONS/
subtract function (Diode1 - Diode2).
ADDRESS
NAME
DESCRIPTION
TABLE 6. PHOTODIODE SELECT MODE; BITS 2 AND 3
b1xxx_xxxx
bx1xx_xxxx
sync_iic
clar_int
Writing a logic 1 to this address bit ends
the current adc-integration and starts
another. Used only with External Timing
Mode.
Writing a logic 1 to this address bit
clears the interrupt.
BITS 3:2
0:0
0:1
MODE
Mode0. ADC integrates or converts Diode1 only. Current
is converted to an n-bit unsigned data.*
Mode1. ADC integrates or coverts Diode2 only. Current is
converted to an n-bit unsigned data.*
1:0
MODE3. A sequential Mode0 then Mode1 operation. The
Command Register 00(hex)
The Read/Write command register has five functions:
1:1
difference current is an (n-1) signed data.*
No operation.
(1) Enable; Bit 7.This function either resets the ADC or
enables the ADC in normal operation. A logic 0 disables
ADC to reset-mode. A logic 1 enables adc to normal
operation.
TABLE 3. ENABLE
* n = 4, 8, 12,16 depending on the number of clock cycles
function.
(5) Width; Bits 1 and 0. This function determines the number
of clock cycles per conversion. Changing the number of
clock cycles does more than just change the resolution of
BIT 7
0
1
OPERATION
Disable ADC-core to reset-mode (default)
Enable ADC-core to normal operation
the device. It also changes the integration time, which is the
period the device’s analog-to-digital (A/D) converter samples
the photodiode current signal for a Lux measurement.
TABLE 7. WIDTH
(2) AdcPD; Bit 6. This function puts the device in a power
down mode. A logic 0 puts the device in normal operation. A
logic 1 powers down the device.
TABLE 4. adcPD
BITS 1:0
0:0
0:1
1:0
NUMBER OF CLOCK CYCLES
2^16 = 65,536
2^12 = 4,096
2^8 = 256
BIT 6
0
OPERATION
Normal operation (default)
1:1
2^4 = 16
1
Power Down
Control Register 01(hex)
The Read/Write control register has three functions:
(3) Timing Mode; Bit 5. This function determines whether the
integration time is done internally or externally. In Internal
Timing Mode, integration time is determined by an internal
dual speed oscillator (fosc), and the n-bit (n = 4, 8, 12,16)
counter inside the ADC. In External Timing Mode, integration
time is determined by the time between two consecutive
(1) Interrupt flag; Bit 5. This is the status bit of the interrupt.
The bit is set to logic high when the interrupt thresholds have
been triggered, and logic low when not yet triggered. Writing
a logic low clears/resets the status bit.
TABLE 8. INTERRUPT FLAG
external-sync sync_iic pules commands.
TABLE 5. TIMING MODE
BIT 5
OPERATION
BIT 5
0
1
OPERATION
Interrupt is cleared or not triggered yet
Interrupt is triggered
0
1
Internal Timing Mode. Integration time is internally
timed determined by fosc, REXT, and number of clock
cycles.
External Timing Mode. Integration time is externally
timed by the I2C host.
(2) Range/Gain; Bits 3 and 2. The Full Scale Range can be
adjusted by an external resistor Rext and/or it can be
adjusted via I2C using the Gain/Range funtion. Gain/Range
has four possible values, Range(k) where k is 1 through 4.
Table 9 lists the possible values of Range(k) and the
(4) Photodiode Select Mode; Bits 3 and 2. This function
controls the mux attached to the two photodiodes. At Mode0,
the mux directs the current of Diode1 to the ADC. At Mode1,
the mux directs the current of Diode2 only to the ADC.
8
resulting FSR for some typical value R EXT resistors. When
Gain/Range is set to Range1 or Range2, the fosc runs at
327kHz. When Gain/Range is set to Range3 or Range4 fosc
runs at twice the rate at 655kHz. The automatic fosc
adjustment feature improves signal-to-noise ratio for low Lux
measurements.
FN6221.1
November 17, 2011
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